Sr. FPGA Engineer, Amazon Leo
Amazon Kuiper Manufacturing Enterprises LLC•3h ago
United StatesOnsite$159.2K–$215.3KFull-timeSenior Level7+ yrs exp
H-1B verified · 2310 LCAs
- Amazon's Low Earth Orbit (LEO) initiative is building next-generation satellite communication systems to deliver high-speed broadband connectivity globally. Our silicon group develops cutting-edge FPGA prototypes and ASIC designs for advanced satellite communication systems. Position Overview: We are seeking an experienced Sr. FPGA Engineer to join our LEO silicon team. This role will contribute to the design, development
- verification of FPGA-based prototypes for our satellite communication systems, including transmit (Tx) and receive (Rx) signal processing chains. Key Responsibilities: - Lead FPGA design and implementation for complex digital signal processing systems in satellite communication applications - Drive FPGA projects through the complete product development lifecycle from architecture to production - Design, implement
- optimize DSP algorithms on FPGA platforms - Perform hands-on lab work including hardware bring-up, debugging
- validation - Collaborate with ASIC design teams to support RTL development and verification - Mentor junior engineers and provide technical leadership on FPGA best practices - Work with cross-functional teams including system architects, software engineers
- hardware engineers Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder)
- lawfully admitted into the U.S. as a refugee or granted asylum.
- Bachelor's degree in Electrical Engineering or a related field - 7+ years of FPGA development experience - Proven track record of completing full FPGA product cycles from concept through production - Strong Digital Signal Processing (DSP) background with experience implementing DSP algorithms in hardware - Excellent lab and debugging skills with experience in hardware bring-up and troubleshooting - Proficiency with FPGA design tools (Xilinx Vivado, Intel Quartus
- similar) - Strong knowledge of HDL languages (Verilog, VHDL, SystemVerilog) - Experience with high-speed interfaces (PCIe, Ethernet, SERDES, etc.)
- Experience with communication systems or RF signal processing - Knowledge of satellite communication protocols and standards - Experience with FPGA prototyping for ASIC development - Familiarity with scripting languages (Python, TCL, Perl) - Experience with version control systems and CI/CD workflows - Strong problem-solving skills and ability to work in a fast-paced environment Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability
- other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications
- location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off
- parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits . USA, WA, Redmond - 159,200.00 - 215,300.00 USD annually
Required skills
FPGADigital Signal ProcessingXilinx VivadoIntel QuartusVerilogVHDLSystemVerilogPCIeEthernetSERDESPythonTCLPerl