ASIC Engineer

Responsibilities: -Execute Scan insertion, Scan DRC check and debug. review DRC reports, debug and resolve DRCs -Tmax pattern generation, Optimize ATPG patterns and improve Fault coverage, check and debug ATPG DRCs -Knowledge of Codec/EDT architecture, debug scan issues indepedently/with minimum supervision -Verify ATPG tests in Zero delay and SDF annotated simulations -Debug simulation failures in VCS, Verdi and other simulators Requirements: -B.Tech / M.Tech (preferred) with 1-3 years of experience in DFT -Strong knowledge of DFT architecture, methodologies and structural debug concepts: JTAG, IEEE1500, Scan tests debug -Experience in executing DFT for multi multimillion gate multi clock domain SoCs -Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level -Experience in using simulators and waveform debugging tools such as VCS and Verdi -Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC -Knowledge of Python, , Shell scripting, Makefiles, TCL -Excellent problem-solving skills and highly self-motivated.

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