Senior Physical Design Engineer for Core IP

As a member of CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency.

Our core designs are present in nearly all segments of intel's compute roadmap. As a Senior Physical Design Engineer for Core IP your responsibilities include: Synthesis and Place and Route using industry standard tools for high speed CPU core design Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure Develop strategies to deliver reproducible design convergence results Help to create and refine synthesis flow for the project team, Develop and recommend better design method practices to enable better synthesis convergence The ideal candidate will exhibit behavioral traits that demonstrate : Willingness to work with others in a highly complex decision space Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule Excellent verbal and written communication and collaboration skills Qualifications: Minimum qualifications are required to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Note: This position is not eligible for Intel immigration sponsorship. Minimum Experience and Qualifications: Bachelors in Computer/Electrical Engineering or related field with 10+ years of relevant work experience.

Or a Masters in the same filed with 5 + years of relevant work experience. You must have 10+ years of experience in: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure PV convergence (including static timing and power analysis) Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g.

Perl, Python, Ruby) Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP Preferred Experience and Qualifications: Physical design best known practices concerning floor-planning, routing techniques, clock distribution Static Timing Analysis, Noise analysis, and reliability verification techniques RTL to GDS methodologies and formal equivalence Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus) Perform CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements Generate and verify timing constraints while addressing timing violations at the chip or block level for CPU cores Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Business group: Intel makes possible the most amazing experiences of the future.

You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges.

Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.

We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.