SOC Timing Analysis (STA) Engineer ,HBM

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology.

We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry.

You will be part of the Heterogeneous Integration Group (HIG), owning chip-level static timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, design for test (DFT), verification, and product teams to ensure timing integrity from initial design through tape-out.

This is a hands-on senior technical role focused on chip-level static timing analysis ownership, timing closure, methodology development, and pre- and post-silicon timing correlation. Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off, covering all timing checks including setup, hold, recovery, removal, and data-to-data across all process corners, operating modes, and voltage and temperature conditions.

Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC) for all clock domains, reset trees, high-bandwidth memory (HBM) physical interfaces, Joint Test Action Group (JTAG), memory built-in self-test (MBIST), design for test (DFT), and configuration logic, ensuring sign-off quality and reuse across design generations.

Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, timing engineering change orders (ECOs), and close collaboration with physical design teams on placement, clock tree synthesis (CTS), and routing to meet timing targets.

Perform multi-mode, multi-corner (MMMC) timing analysis including setup and hold closure, clock domain crossing (CDC) timing, and application of on-chip variation derates (OCV, AOCV, POCV) appropriate for advanced technology nodes. Lead signal integrity and crosstalk analysis, identify noise-induced timing violations, and work with physical design teams to implement mitigation strategies, while conducting DFT timing analysis including scan chain timing, automatic test pattern generation (ATPG) mode constraints, MBIST timing closure, and JTAG interface timing.

Partner with RTL and architecture teams to provide early static timing analysis feedback on micro-architectural decisions, clock architecture, timing budgets, and power and area tradeoffs, and develop and maintain automation scripts and flows in Python and Tcl for constraint generation, timing report extraction, waiver management, quality of results dashboards, regression tracking, and sign-off readiness reporting.

Perform post-silicon timing correlation by analyzing silicon measurement data against pre-silicon predictions, identifying systematic discrepancies, feeding learnings back into timing models, tool settings, and methodology updates, and engaging directly with electronic design automation tool vendors to evaluate new features, resolve tool issues, and drive methodology enhancements.

Define and drive static timing analysis methods, sign-off standards, and timing closure rules across the organization. Lead readiness reviews and tape-out sign-off gates. Mentor junior engineers and contribute to documentation, timing reports, constraint specs, and block-level timing budgets.

Collaborate with Physical Compose, RTL, Verification, DFT, Product Engineering, and Test teams to meet timing requirements through all compose phases