Mixed Signal Design Verification Engineer
Top focus
Job Description
The Role and Impact Join our team as a Mixed Signal Design Verification Engineer and play a critical role in ensuring the functionality and quality of mixed signal logic components. In this position, you will develop and execute verification methodologies that directly contribute to the success of cutting-edge technologies and meet our rigorous performance, power, and reliability standards.
By collaborating with architects and designers, you will help shape and verify complex microarchitectural features that are at the forefront of innovation. This is an opportunity to work in a dynamic and fast-paced environment where your contributions will influence the next generation of advanced technologies
Key Responsibilities
Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure designs meet specification requirements. - Develop and execute IP verification plans, test benches, and verification environments to achieve comprehensive coverage aligned with mixed signal microarchitecture specifications. - Define and run system simulation models to verify design functionality, analyze power and timing, and uncover potential bugs. - Root cause, debug, and resolve issues in pre-silicon environments, implementing corrective measures to address failing tests. - Collaborate closely with digital and analog architects, RTL developers, and physical design teams to improve verification methodologies and meet functional, performance, and power goals. - Document test plans and drive technical reviews with design and architecture teams to ensure robust verification coverage. - Maintain and enhance existing functional verification infrastructure and methodologies to support ongoing innovation and efficiency improvements
Qualifications
Minimum Qualifications - Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering or a related field. - 0-3 years of relevant industry experience with a Bachelor's degree, 1+ years with a Master's degree, or 0 years with a PhD. - Proficiency in Verilog, System Verilog, and knowledge of Universal Verification Methodology (UVM). - Hands-on experience in developing verification environments, defining test plans, and executing verification strategies. - Hands-on experience in simulation and debugging tools such as VCS and Verdi. - Demonstrated ability to analyze and debug RTL designs and address verification challenges
Preferred Qualifications
- Knowledge of low-power design techniques, including Unified Power Format (UPF) and clock gating. - Familiarity with multiple clock domain designs and state machine design concepts. - Knowledge of integrating BFMs and checkers. - Exposure to coding coverage metrics, assertions
- formal verification techniques. - Knowledge of scripting languages such as Python, Perl
- Make for automation and process optimization. - Understanding of verification methodologies like AVM, RVM
- eRM, with a preference for UVM. - Experience with IO design and validation methodologies for analog, digital
- mixed-signal circuits would be a great addition. - Familiarity with protocols such as PCI-Express, USB, Display Port, Ethernet, DDR, AMBA, JTAG
- Explore this exciting opportunity to make a meaningful impact on the development of next-generation technologies.
- Apply now to join a team that values innovation, collaboration, and excellence.
- Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation
- any other characteristic protected by local law, regulation
- Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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