Timing & Power Analysis CAD Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.

What You Can Expect Develop, maintain, and enhance PrimeTime-STA & PrimePower-based power signoff flows within Marvell's M1DP CAD platform. Solid understanding of STA flows including dealing with hierarchical designs Understanding of using Hyperscale & Context models for Hierarchical STA analysis Solid understanding of power estimation flows (average and time-based) Enable and support In-Design Timing & Power flows for timing/power-aware optimization during physical implementation.

Collaborate with Physical Design and Front-End teams to set up FSDB/activity files, UPF/CLP power intent, and SAIF/vector annotation for accurate power computation. Develop and maintain glitch analysis and optimization flows , including configuration of glitch-aware datapath optimization settings is a plus Generate, validate, and deliver power analysis reports (dynamic, leakage, glitch) to design teams across multiple ASIC projects by building power dashboard Experience with PrimePower RTL 2.0 adoption for early-stage power estimation, enabling designers to identify and resolve power issues before gate-level analysis is plus Interface with EDA vendors to evaluate new tool features, report bugs, and drive tool improvements.

Develop automation scripts (Tcl, Python) to streamline timing & power flow execution, debug, and reporting. Support tapeout activities by ensuring power & timing signoff closure across blocks and full-chip designs. Contribute to knowledge sharing, documentation, and training for timing & power CAD flows across global teams.

What We're Looking For B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field. 6 to 10 years of hands-on experience in CAD flow development or power analysis in the semiconductor industry (level-dependent).

Proven experience with Synopsys PrimeTime & PrimePower (gate-level and/or RTL-level power analysis). Solid understanding of timing concepts Understanding of advanced node timing effects and variation formats (LVF, POCV & AOCV etc) Experience in correlating timing QoR between P&R and signoff timing engine Solid understanding of power analysis concepts: dynamic power, leakage, glitch power, clock gating efficiency (CGE).

Experience with FSDB/VCD/SAIF activity file generation and annotation flows. Familiarity with UPF/CPF power intent and multi-voltage design methodologies. Proficiency in Tcl scripting for CAD flow development and automation. Working knowledge of Physical Design flows (P&R) and their interaction with power & timing signoff.

Strong analytical and problem-solving skills; ability to debug complex power analysis issues. Good verbal and written communication skills in English; ability to collaborate with global teams. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.

We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law.

Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RS1